1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having externally controllable data input and output mode.
2. Description of the Related Art
A semiconductor memory device includes storage elements. A user can write data into or read data out from these storage elements. That is, a user can input or output data to and from the memory device. A plurality of data items can be simultaneously input and output. The number of data items simultaneously input to and output from the memory device depends on the input and output mode set by the manufacturer during manufacturing. For example, the manufacturer can set the input and output mode to ×4, ×8, and ×16. When the input and output mode is set to ×4, the number of data items simultaneously input to and output from the memory is 4. When the input and output mode is set to ×8, the number of data items simultaneously input to and output from the memory is 8. When the input and output mode is set to ×16, the number of data items simultaneously input to and output from the memory is 16. The input and output mode for a given memory device is set when the semiconductor memory device is designed. An input and output mode controlling circuit sets the input and output mode.
FIG. 1 is a circuit diagram of the input and output mode controlling circuit included in a conventional semiconductor memory device. Referring to FIG. 1, a conventional input and output mode controlling circuit 101 includes a first input and output mode setting unit 111 and a second input and output mode setting unit 112. The first input and output mode setting unit 111 sets the mode to ×16. The second input and output mode setting unit 112 sets the mode to ×4. When a signal P16 is at a logic high level, the input and output mode of the semiconductor memory device 101 is set to ×16. When a signal P4 is at the logic high level, the input and output mode of the semiconductor memory device 101 is set to ×4. When the signals P4 and P16 are both at logic low levels, the input and output mode of the semiconductor memory device 101 is set to ×8. The signals P4 and P16 are never both simultaneously at logic high levels.
The first input and output mode setting unit 111 includes a pad 121, an NMOS transistor 131, a PMOS transistor 141, and inverters 151 through 153. The second input and output mode setting unit 112 includes a pad 122, an NMOS transistor 132, a PMOS transistor 142, and inverters 154 through 156. When the input and output mode of the semiconductor memory device 101 is to be set to be ×16, the pad 121 is grounded. When the input and output mode of the semiconductor memory device is set to be ×4, the pad 122 is grounded. The NMOS transistors 131 and 132, and the PMOS transistors 141 and 142, are always turned on by providing a supply voltage Vcc to the semiconductor memory device 101. The PMOS transistors 141 and 142 are smaller than the NMOS transistors 131 and 132.
When the pad 121 is grounded, the voltage level of node N1 is decreased to the level of a ground voltage GND. Accordingly, the signal P16 is at the logic high level. When the pad 121 floats, the voltage level of the node N1 is increased to the level of the supply voltage Vcc. Accordingly, the signal P16 is at the logic low level. When the pad 121 floats and the pad 122 is grounded, the voltage level of the node N2 is decreased to the level of the ground voltage GND. Accordingly, the signal P4 is at the logic high level. When the pad 122 floats, the voltage level of the node N2 is increased to the level of the supply voltage Vcc. Accordingly, the signal P4 is at the logic low level. When the pads 121 and 122 both float, the signals P4 and P16 are at the logic low level. Namely, the input and output mode of the semiconductor memory device is set to ×8.
In the conventional semiconductor memory device 101, the input and output mode cannot be changed after the device is packaged. The fixed input and output mode leads to the following problems. First, productivity is lowered because the semiconductor memory device must be tested in each input and output mode. Second, test efficiency is reduced because the driving capability depends on the input and output mode of the semiconductor memory device. Third, since specifications are classified during the evaluation of the semiconductor memory device, it is difficult to completely characterize the semiconductor memory device in each input and output mode.